1. Field of the Invention
This invention relates to computer system power management and, more particularly, to clock tree starting and stopping.
2. Description of the Related Art
As computer systems have become more powerful, power management has become a more critical part of the overall system design. This may be especially true for systems that have portable applications. To reduce the power consumed by a computer system, many computer systems employ processors that are capable of entering a standby or low power mode when there is no demand on the processor for a specified duration. In addition, to further decrease the power consumed by a system, the same low power modes may be implemented for the chipsets that are associated with the processor.
There are many ways to place a system component into a low power mode. For integrated circuits using complementary metal oxide semiconductor (CMOS) technology, the time during a transition from a logic one to a logic zero and from a logic zero to a logic one typically consumes the most power since the most current is flowing in a particular circuit. Thus, one method of decreasing system power is to halt unnecessary switching. In clocked systems, the clock signal may be the source of most of the unnecessary switching during idle processing times.
When a clock signal is distributed throughout a system, the resulting clock distribution network is commonly referred to as a clock tree. Many systems take advantage of idle processing time by shutting down portions of the clock tree using clock gating techniques. However, depending on the complexity of the clock tree, it may be difficult to shut down portions of the clock tree due to factors such as added gate delays caused by multiple clock gating circuits. Alternatively, in some systems the entire clock tree is shut down. However, in systems that employ a clock generation circuit such as a phase locked loop (PLL), shutting down the entire clock tree may cause unacceptable delays when the system clock must be restarted.
Various embodiments of a circuit and method for stopping a clock tree while maintaining PLL lock are disclosed. In one embodiment, a clock circuit includes a locked loop circuit, such as a PLL, for example and a clock tree distribution network. The locked loop circuit is configured to receive an input clock signal and to generate a PLL output clock depending upon a feedback signal. The clock tree distribution network is coupled to the locked loop circuit and is configured to convey the PLL output clock to a plurality of clocked circuit elements such as flip-flops. The clock circuit further includes a gating circuit and a feedback delay circuit. The gating circuit is coupled between the locked loop circuit the clock tree distribution network. The gating circuit is configured to selectively inhibit the PLL output clock from clocking the clock tree distribution network. The feedback delay circuit is coupled to receive the PLL output clock and to generate the feedback signal which represents a delayed version of the PLL output clock. The feedback delay circuit is configured to provide the feedback signal during operation including when the gating circuit inhibits the PLL output clock from clocking the clock tree distribution network.
In one particular implementation, the delayed version of the PLL output clock is derived by adding a predetermined delay to the PLL output clock. The predetermined delay is substantially equal to a delay caused by propagation of the PLL output clock through the clock tree distribution network. The delayed version of the PLL output clock is derived by a combination of propagating the PLL output clock through a predetermined number of feedback logic gates and by a predetermined routing of signal traces connecting those feedback logic gates.